Description: sdram控制器
这里考虑将SDRAM控制器结合目前项目开展来做相应的模块,而不做SDRAM通用控制器,这样也是考虑了FPGA的器件资源而采取的措施。同时编写的逻辑简单,没有多余的逻辑资源有利于提高控制器的速度,满足最后的设计要求。-SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, as well as consider the FPGA device resources and the measures taken. While the preparation of simple logic, the logic is no spare resources to improve the speed controller to meet the final design requirements. Platform: |
Size: 3072 |
Author:林博 |
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Description: 精简的sdram读写控制器例子,适用于数据采集系统,verilog,只支持burst方式的读写-streamlined read and write SDRAM controller example, applied to the data acquisition system, Verilog. only supports burst mode read and write Platform: |
Size: 153600 |
Author:梁文锋 |
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Description: SDRAM控制器Verilog员代码,数据链路模块,完成和顶层模块的数据交换-SDRAM controller member Verilog code, data link module, Top module completed and the data exchange Platform: |
Size: 2048 |
Author:陈建勇 |
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Description: 已经成功的FPGA 控制的SDRAM控制器代码.只要修改你需要的宽度就可以了.-FPGA has been successfully controlled by SDRAM controller code. As long as you need to modify the width of it. Platform: |
Size: 187392 |
Author:chen qiming |
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Description: 可以用的通用SDRAM控制器,可以用在FPGA上,是SDR类型的-Can use the generic SDRAM controller can be used in the FPGA, the SDR is the type of Platform: |
Size: 9216 |
Author:郑宏超 |
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Description: sdram控制器的开发程序,还有文档,可以参考以下-SDRAM controller development process, there is a document, you can refer to the following Platform: |
Size: 776192 |
Author:王鹏 |
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Description: 在ISE开发环境下的单速率SDRAM简单读写控制器设计,用的是verilog硬件描述语言-ISE development environment in a single-rate SDRAM controller read and write simple design, using the verilog hardware description language Platform: |
Size: 157696 |
Author:小桂 |
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Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory.
This code is Verilog.
This code is based Xilinx FPGA Playform. Platform: |
Size: 488448 |
Author:peace |
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Description: 双端口SDRAM控制器,将SDRAM虚拟成两个端口,已经在ALTER DE2开发板的硬件上验证通过,采用Verilog HDL语言编写。-Dual-port SDRAM controller, SDRAM virtual into two ports, have ALTER DE2 development board hardware verification by using the Verilog HDL language. Platform: |
Size: 11264 |
Author: |
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Description: SDRAM 控制器的 verilog 源代码, 针对Micron 的SDRAMS设计,支持全部的指令, 已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SDRAM controller verilog source code, for Micron' s SDRAMS designed to support all of the instructions, the logic has been verified, and actually used in chip design, as a module to work. Platform: |
Size: 9216 |
Author:Jerd Hu |
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